Homework 6

EE 3320 Digital Circuits
Fall 2014
Homework 6
November 18, 2014
1. (12 points) Convert the given Mealy state diagram to Moore state diagram and implement the
resulting Moore machine using D flip-flops and any logic gate from table given below. Choose the
most appropriate logic gates and flip-flops so that the circuit can be run at a clock speed of 50 MHz
(period of 20ns). Write the “Name” of each library element you choose on the given schematic
diagram.
After designing the circuit, it was implemented on a PC board and the actual clock skew was
measured to be 6ns. Will your circuit work as designed? If it is not working at the designed speed of
50 MHz, will it work at 30 MHz? Show all work and justify all your answers.
B
1/0
1/0
1/0
A
D
Name
2-input AND
AND_A
AND_B
AND_C
NAND_A
NAND_B
OR_A
OR_B
OR_C
NOT_A
NOT_B
DFF_A
DFF_B
1/1
0/0
0/0
C
2-input NAND
0/0
2-input OR
0/1
tp
Logic Circuit
Inverter
D Flip-flop
min
2.5
3
2.5
1.5
2
2.5
2.5
3
2.5
1.0
4
2.5
tsu
max
3.5
4
4.5
3
3.5
4
5
6.5
4
2
5
4
th
min
max
min
max
2
4
4
6
0
1
1
1.5
2. (8 points) For the state table given below reduce the number of states. The state table has 12 states, 2
inputs (s1 and s0), and 2 outputs (x1 and x0). Show all work and give equivalent states if there are any.
Present
State
0
1
2
3
4
5
6
7
8
EE3320
s1 s0
00
0
0
8
0
8
8
0
0
8
Next State
s1 s0
s1 s0
01
10
8
2
3
2
5
2
3
7
5
7
5
2
3
2
3
7
0
7
1
Outputs
s1 s0
11
1
1
6
1
4
4
6
6
4
x1 x0
00
01
10
11
01
11
11
10
00
Fall 2014
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