CHAPTER 5 OTHER JUNCTIONS IN SEMICONDUCTORS

CHAPTER 5
OTHER JUNCTIONS IN
SEMICONDUCTORS
© Nezih Pala [email protected]
EEE 6397 – Semiconductor Device Theory
1
Metal - semiconductor junctions
Metal-semiconductor junctions can be designed to have similar rectification properties to
the p-n junction properties. These rectifying semiconductor-metal junctions are called
Schottky diodes.
For some applications metal-semiconductor junctions can be used instead of p-n junctions
for rectification.
Metal-semiconductor junctions are also important to form ohmic (non-rectifying) contacts
in microelectronic device fabrication.
Фm: Metal work function: Energy required to remove
an electron at the Fermi level to the vacuum outside
the metal.
Фs: Semiconductor work function
 : Electron affinity: Energy required to move an
electron from bottom of the conduction band to the
vacuum.
© Nezih Pala [email protected]
EEE 6397 – Semiconductor Device Theory
2
Schottky Barrier -4
The Schottky barrier height for n- or p-type semiconductors depends upon the metal and
the semiconductor properties. This is true for an ideal case. It is found experimentally that
the Schottky barrier height is often independent of the metal employed.
© Nezih Pala [email protected]
EEE 6397 – Semiconductor Device Theory
3
Schottky contacts
When a metal with work function qФm is brought in contact
with a semiconductor having a work function qФs, charge
transfer occurs until the Fermi levels align at the
equilibrium.
For an n-type semiconductor with qФs< qФm :
•Semiconductor Fermi level is initially higher.
•Electron energies in semiconductor must be lowered to align
the Fermi levels.
•Electrons are transferred into the metal, leaving behind a
depletion region filled with ionized (positively charged)
donors.
•Depletion width and the junction capacitance can be
calculated similar to the case of p+ - n junction.
© Nezih Pala [email protected]
EEE 6397 – Semiconductor Device Theory
4
Schottky contacts -2
Contact (built in) potential qV0 = qФm - qФm
Schottky barrier qФB = qФm – q χ
© Nezih Pala [email protected]
EEE 6397 – Semiconductor Device Theory
5
Schottky contacts -3
For a p-type semiconductor with qФm< qФs :
•Semiconductor Fermi level is initially lower.
•Electron energies in semiconductor must be raised to align
the Fermi levels.
•Holes are transferred into the metal, leaving behind a
depletion region filled with ionized (negatively charged)
acceptors.
•Depletion width and the junction capacitance can be
calculated similar tot eh case of n+ - p junction.
© Nezih Pala [email protected]
EEE 6397 – Semiconductor Device Theory
6
Schottky contacts under forward bias
When a forward bias V is applied (positive to metal
and negative to the n-type semiconductor) , the
contact potential is reduced form V0 to V0-V.
Electrons in the semiconductor conduction band
can diffuse across the depletion region to the
metal.
This gives rise to a forward current (metal to
semiconductor) through the junction.
The resulting diode equation is similar in form to that of p-n junction:


I  I 0 eqV / kT  1
© Nezih Pala [email protected]
EEE 6397 – Semiconductor Device Theory
7
Schottky contacts under reverse bias
When a reverse bias V is applied (negative to metal
and positive to the n-type semiconductor) , the
contact potential is raised to V0 +V.
Electron flow from semiconductor to metal
becomes negligible.
Electron flow from metal to the semiconductor is
retarded by the barrier ФB = Фm – χ .
The reverse saturation current I0 is not the same as it was
for the p-n junction. It is related to the height if the barrier
ФB.
I0  e
© Nezih Pala [email protected]
 qB / kT
EEE 6397 – Semiconductor Device Theory
8
Ohmic contacts
Ohmic contacts occur when the induced
charge in the semiconductor during the
Femi level alignment is the majority
carriers.
Barrier for carriers is small and can be
overcome easily by a small voltage.
No depletion region occurs in the
semiconductor since Fermi level alignment
calls for accumulation of majority carriers
in the semiconductor.
Ohmic contacts are formed by doping
the semiconductor very heavily.
© Nezih Pala [email protected]
EEE 6397 – Semiconductor Device Theory
9
Ohmic contacts -2
ФM > ФS
n-type
Semiconductor
Rectifying
p-type
Semiconductor
Ohmic
ФM < ФS
Ohmic
Rectifying
© Nezih Pala [email protected]
EEE 6397 – Semiconductor Device Theory
10
Fermi level pinning
Unlike p-n junctions which occur in a single piece of
crystal, a Schottky junction includes a termination
end of semiconductor crystal.
The semiconductor surface contains surface states
due to the incomplete covalent bonds.
The surface states pin the Fermi level at a certain
energy.
That results a fixed barrier height independent of the
metal forming the junction.
ФB≈0.7 ~0.9 eV for metal – n-GaAs junction
© Nezih Pala [email protected]
EEE 6397 – Semiconductor Device Theory
11
Comparison of Schottky and p-n diodes
© Nezih Pala [email protected]
EEE 6397 – Semiconductor Device Theory
12
Example
Calculate the capacitance for the following Si n+-p junction.
Na=1015 cm-3,
area=0.001cm2,
reverse bias=-1V, -5V, -10V.
Plot 1/C2 vs VR. Demonstrate that the slope yields Na. Repeat calculations for Na=1017
cm-3. Since the doping in not specified on the n+ side, use suitable approximation.
© Nezih Pala [email protected]
EEE 6397 – Semiconductor Device Theory
13
Example
S
C
A
W
 2 V0  N a  N d  
W



q
N
N

a d 
1
2
For n+-p junction, Nd>>Na
 2  (V0  VR ) 
W 

qN a


1
2
CA
qN a S
2(V0  VR )
We need to know V0. We can not use the usual eqn since we don't know Nd!!!
V0  ( Eip  EFp )  ( EFn  Ein )
p  ni e
( Eip  EFp ) / kT
© Nezih Pala [email protected]
For n+ the second term is ~0.55eV
 Na 
 Eip  EFp  kT ln  
 ni 
 Na 
V0  0.55  0.0259 ln  
 ni 
EEE 6397 – Semiconductor Device Theory
14
Example
1
1 2V0  VR 
2
V0  VR 
 2
 2
2
C A qN a S
A qN a S
This means that the slope of 1/C2 versus VR gives the Na if the material type (dielectric
constant) and the area are known.
© Nezih Pala [email protected]
EEE 6397 – Semiconductor Device Theory
15
Insulator-Semiconductor Junctions
Earlier, we have called materials with large bandgaps insulators. Usually these materials
don’t have high crystalline quality and are difficult to dope. These materials have very
high resistivity and are used to isolate regions to prevent current flow.
Most insulator-semiconductor combinations involve structures that are not latticematched. In most cases the insulator and the semiconductor do not even share the same
basic lattice type.
In this section we will briefly review a
few such combinations. Important
issues in these junctions are listed in the
figure. The key issues here revolve
around producing an interface with very
low density of trapping states and low
interface leakage.
© Nezih Pala [email protected]
EEE 6397 – Semiconductor Device Theory
16
Insulator-Silicon Junction -1
The most important junction in solid state electronics is the SiO2-Si system. In spite of the
severe mismatch between SiO2 structure and Si structure, the interface quality is quite
good.
Midgap interface density as low as 1010 eV−1 cm−2 can be readily obtained. The ability to
produce such high-quality interfaces is responsible for the remarkable success of the
metaloxide-silicon (MOS) devices. Due to the low interface densities, there is very little
trapping of electrons (holes) at the interface so that high-speed switching can be
predictably used.
It has to be recognized though that the interface is still rough with islands with a height of
5 A over lateral extents of ∼50 A . Typical electron mobility in Si MOSFETs is ∼600 cm2/(V ·
s) compared to a mobility of ∼1100 cm2/(V · s) (300 K) for bulk pure Si. We will discuss the
MOS structure in detail later.
© Nezih Pala [email protected]
EEE 6397 – Semiconductor Device Theory
17
Insulator-Silicon Junction -2
Silicon nitride (Si3N4) is another important film that forms modest-quality junctions with
Si. Silicon nitride can be used in a metal-insulator-semiconductor device in Si technology,
but its applications are limited. The film is used more as a mask for oxidation of the Si
film. It also makes a good material for passivation of finished devices. Silicon oxy-nitride
on the other hand forms high-quality interfaces with silicon and can be used in FETs.
Although not an insulator or a metal, we include polycrystalline silicon (“poly”) in this
chapter because of its importance in Si technology. Polysilicon can be deposited by the
pyrolysis (heatinduced decomposition) of silane:
SiH4 −→ Si + 2H2
Depending upon the deposition temperature, micro crystallites of different grain sizes
are produced. Typical grain size is ∼ 0.1 μm.
Poly films can be doped to low resistivity to produce useful conductors for a number of
applications. Poly is often used as a gate of an MOS transistor, as a resistor, or as a link
between a metal and the Si substrate to ensure an ohmic contact.
© Nezih Pala [email protected]
EEE 6397 – Semiconductor Device Theory
18
`