How to Develop a Qualification Test Plan for RoHS Products

How to Develop a Qualification Test Plan for RoHS Products
Mike Silverman, Ops A La Carte LLC
Fred Schenkelberg, Ops A La Carte LLC
Craig Hillman, PhD, DfR Solutions
Key Words: RoHS, qualification, underplate, delamination
The subject matter we consider in this paper are the
significant reliability uncertainties around Lead-Free Solder
and how to best consider these risks and mitigate them so as
not to take a hit in the area of reliability during the lead-free
Like the rest of the electronics industry, your products
will transition to Restriction of Hazardous Substances (RoHS)
compliance. This includes the transition to Lead-Free Solder,
and at this time, there are significant reliability uncertainties
around Lead-Free Solder. Even if your product does not need
to be compliant, the materials and processes that make up your
product are changing. During this time of rapid transition,
there is a significant new body of knowledge to understand to
determine the areas of greatest risk to the reliability of your
product. In this paper, we will highlight a few of these
significant risk areas and how to best mitigate these risks
during the transition.
Lead-free solder materials have been used in the
electronics industry for over 60 years and therefore the
processing conditions and their impact on materials and
reliability are well understood. Converting to lead-free
products and processes introduces many risks some of which
are better understood than others. Even though the deadline of
July 1, 2006 [1] came and went, many companies are still
struggling with this issue and are either still trying to become
compliant, or have developed substandard methodologies to
meet the deadline, only to find out that they created a ticking
time bomb of reliability that is just waiting to go off.
This paper explores the main risks involved and shows
how to evaluate the risks and set up qualification programs to
mitigate these risks. If these steps are taken, the reliability of
lead-free products and processes can yield products just as
reliable as their leaded counterparts.
1.1 Nomenclature
RoHS: Restriction of Hazardous Substances
Sn: Tin
Pb: Lead
SnPb: Tin-Lead formulation of solder
MSL: Moisture Sensitivity Level
Pb-Free or Lead-Free: Part of the RoHS directive [1] is to
restrict the use of lead on electronic systems.
SnPb solder materials have been used in the electronics
industry for over 60 years and therefore the processing
conditions and their impact on materials and reliability are
well understood.
Converting to Pb-free materials and
processes introduces many risks some of which are better
understood than others. The following table describes some
of the changes inherent with Pb-free, the failure mechanisms
they may induce and the testing/inspection procedures used to
screen for them. The test criteria called out in this Pb-free
qualification document are intended to screen for many of
these potential failure mechanisms.
Area of
Heat damage
Impacted Item
Failure Mechanism
Plastic IC packages,
optocouplers, other
polymer based
All passive components,
circuit boards
Popcorn delamination at
higher reflow
temperatures. Heat damage
of IC packages
Cracking, dielectric
breakdown (capacitors),
PCB delamination,
warping, or via cracking
Cold joints or weak joints
fracture in use environment
Cracked solder joints
Poor wetting
All solder joints
Solder fatigue
Solder joints,
particularly on high
CTE components
Solder joints
particularly on higher
mass components
Sn and SnCu plated
Insufficient process
window creates poor
solder joints
Poor solder joints,
damaged components
Incomplete hole fill,
fillet lifting, damage to
Board surface with noclean paste residue
Sn whiskers
Surface mount
process control
Rework process
Wave solder
Solder joint failure during
shipping or dropping
Occasional solder joint
failures in use environment
Joint failures or cracked
vias in use environment
Failed through hole,
cracked vias, weak joints
Shorting between biased
traces in a moist
Table 1a – Pb-Free Risk Table, Failure Mechanisms
Area of
Heat damage
Poor wetting
Solder fatigue
Sn whiskers
Surface mount
process control
Rework process
Wave solder
al migration
Testing Method
Moisture sensitivity
Heat resistance
MIL-STD 202G #210F
Decomposition temp.
Time to delamination
Package planarity
Thermal cycle
Shock test
Precondition and
JEDEC Standard 22A113D
Rework components
followed by reliability
Thermal cycle
Bellcore GR-78CORE
Inspection Technique
Visual inspection
Visual inspection,
functional verification
Wetting balance, visual
inspection, x-sectioning,
lead pull
Electrical continuity
Visual inspection
Electrical continuity
Visual inspection
X-ray, X-section,
Inspection, reliability test
X-ray, X-section,
Inspection, reliability test
Electrical continuity,
visual inspection
Visual and resistance
after 35C/85%RH
exposure at 50V
Table 1b – Pb-Free Risk Table, Inspection Methods
Note: For the board in this study, solder fatigue and
mechanical shock do not seem to have a significant risk factor
and are not recommended for evaluation. This is based on the
assumption of adequate packaging during transport and the
stable operating temperature (very little if any thermal cycling
during use).
2.1 The Approach
The basic approach is to verify adequate qualification of
the individual components has occurred. By requesting and
reviewing detailed vendor data most of the risk for your
product is either identified or reduced. For example, if a
vendor is unable to produce or has inadequate MSL rating test
results, then the risk for popcorning defects is present. With
engineering judgment, considering the processing parameters,
we can decide to conduct proper MSL evaluation to determine
true risk of using the component.
2.2 Qualification Requirements – First Level
This level is reserved for products with lower perceived
risk of failure due to introduction of lead-free materials and
processing. Products determined to be in this level are
relatively simple and constructed exclusively with components
such as passives, through-hole and/or coarse pitch (>0.5 mm)
surface mount leaded packages. Some exceptions may apply
based on specific product application or use environment. To
ensure that all materials can survive the elevated temperatures
expected with lead free assembly, all components must be
evaluated individually prior to assembly. Types of failure
mechanisms being screened for include heat damage, moisture
induced cracking/delamination, poor solderability, and weak
The following information permits the identification of
specific risks and creates a baseline of information on Pb-free
assemblies and processes.
Materials Used
PCB type
PCB Manufacturer
PCBA Assembler (list if sub contracted, In House, sub
PCB glass transition temperature
PCB decomposition temperature
PCB manufacturer certified heat resistance
PCB Thickness
PCB # Layers
1 or 2 side populated
Pad finish type (i.e.ImAg, OSP, etc.)
List the surface mount lead-free alloy (i.e. Sn-3.5Ag0.9Cu)
Solder paste manufacturer and product # (list all
SIR test results from solder paste supplier.
Flux type (no clean, water soluble, etc.)
Wave solder Pb-free alloy
Hand Solder / Rework (Wire) Pb free alloy
Process Information
The information requested below is important to both
supplier quality and reliability engineering in relation to lead
free process and reliability impact. The questions are meant to
establish a baseline for these items relative to initial lead free
process management. The vendor must maintain a consistent
process going forward or inform customer of changes.
1. Is the product built with a single or dual reflow process?
2. List the peak temperature distribution across the
3. Time within 5C of peak.
4. List the time above liquidus temperature.
5. Provide time / temperature reflow profile. Provide
location on PCB / Panel for thermocouple probes (attach
picture / diagram) and temperatures for those locations
during the reflow process.
6. List the minimum peak solder joint temp measured on
board (under highest thermal mass component).
7. Wave solder process flow and maximum solder pot
temperature / duration (if applicable).
8. Soldering iron temperature (Temp +/-) for rework and
hand solder. Maximum allowable hand-solder duration.
Provide general overview of part storage and factory floor
management for components according to MSL level (for
moisture sensitive components).
Detailed part
management is subject to on site audit.
Is nitrogen used in reflow?
Procedures for rework to include inspection criteria and
soldering iron temperature.
Inspection criteria used for lead-free solder joints. This
will include criteria for sub contracted assemblies.
Provide general overview regarding isolation and tracking
of leaded components / materials from Pb-free
components / materials. Detailed part management is
subject to on site audit.
Component Information – Heat Resistance
and not acceptable). Lead plating situations as outlined in
table 1 will require testing according to NEMI/JEITA
recommended procedures: 1) Storing at 60°C/95%RH for
1000 hours note 3 & 4 followed by SEM analysis; 2) Thermal
cycling 1000 times from -55°C/85°C note2 followed by SEM
analysis; and 3) Store at room atmosphere conditions for 1000
hours note 3 & 4 followed by SEM analysis.
Criteria: Maximum allowable whisker length is 50
microns (separate criteria for FFC/FPC/Connector Mating).
All components used to build a Pb-free product must be
rated for temperatures at least 10°C higher than peak assembly
process temperature. Heat resistance testing should be
performed following MIL-STD 202G #210F with 90-120sec
above Pb-free solder liquidus with ≥ 10 seconds at or above
peak (+10C). Deviation for time above liquidus may be
allowed based on process TAL (must be a minimum of 20%
greater than process TAL). MIL-STD-202G #210F should be
followed for wave solder and soldering iron heat resistance.
Components that are hand soldered, reworked, or touched up
should be rated for a soldering iron temperature at least 10°C
higher than process conditions. Recommended min sample
size is 10/lot for 3 lots.
Component Information – Moisture Sensitivity
Determining the moisture level for surface mount
components should be done following J-STD-020C for Pbfree or JEITA ED 4701 (Test Method 301A for Pb-Free).
Components qualified to J-STD-020B may be acceptable if
temperature rating is deemed sufficient. Sample sizes are
defined in the specifications as well as inspection and pass/fail
criteria. A minimum of 3 reflows is required. A minimum of
60 seconds above liquidus or duration 20% higher than actual
reflow process time above liquidus (whichever is longer) is
required. SMT type components that are wave soldered will
follow procedures detailed in JEITA ED 4701 (Test Method
301A for Pb-Free). A minimum of Level 3 (JEDEC) or Level
E (JEITA) is required for all components.
Level 4
components (JEDEC) or Level F/G (JEITA) may be approved
if factory management is considered acceptable. Components
that do meet minimum of Level 4 or above are not acceptable.
Lead Plating
The Pb-free lead plating material is important in
evaluating the risk for tin whiskers. Table 1 outlines
requirements for Tin Whisker testing for plating materials
determined to be a risk. Finer pitch components plated with Sn
based lead finish are most susceptible to shorting due to
whisker growth. A 1.3 μm nickel underplate is preferred for
Sn finishes as this prevents copper diffusion into the Sn which
contributes to compressive stress in the Sn layer (the primary
driving force for Sn whiskers for Cu base material). SnCu
plating is known to be a high risk for Sn whisker growth and
should be avoided when possible (bright Sn is the highest risk
Sample size: 10 per condition. Samples should be taken
from 3 lots, divided equally between each condition (total
samples 30).
Recommended thermal cycle condition: 20C/min, 10 min
dwell at each temperature.
For Cu base material, testing duration for high reliability
application will be 4000 hours for ambient and
temperature / humidity (non-FFC/FPC/Connector
mating). Whisker evaluation will need to take place every
1000 hours.
Testing duration for high reliability application will be for
2000 hours for ambient and temperature / humidity
(FFC/FPC/Connector Mating). Whisker evaluation will
take place after 2000 hours only.
Measurement to be by SEM following NEMI guideline.
Measurement method per NEMI (full length of whisker
must be measured).
Full scan of each pin needs to be performed to find
longest whiskers, while more detailed scan to be
performed on a minimum of 10 pins per device. Detailed
scan must be measured using SEM at 400X minimum,
with magnification up to 4000x for whisker verification.
Sampling of pins needs to be from each side.
Parts that are reflowed through manufacturing process
need to be reflowed through equivalent profile (nonsoldered) prior to Tin Whisker testing. Profile to be
Test details (including any deviations) and reporting
requirement must include SEM images, number of pins
measured per device, inspection method, whisker length
and count reporting. Representative photos of longest
whiskers observed to be provided in a clear reporting
Testing is to be performed on the component part number
to be used.
Testing is required for each manufacturing location /
process used.
In addition to whisker length reporting, minimum
reporting must also include part number(s) tested, base
material, manufacturing location, manufacturing date, lot
# (s), test date(s), plating type (% each element),
thickness, and underplate thickness (if applicable).
Specify whether parts are annealed (including condition).
Post production annealing of 150C for 1 hour is preferred.
All Components EXCEPT: FFC/FPC/Connector Mating End
Lead Pitch
Lead Pitch
> 0.5mm
≤ 0.5mm
(>1.3 μm Ni)
SnAgCu &
Sn (matte)
Reflow or annealing
may help reduce Sn
whisker density
(conflicting industry
For high reliability
applications, testing
may be required for
>0.5mm pitch
Sn (bright)
Unacceptable Unacceptable Semi-bright Sn should
be treated similar to
FFC/FPC/Connector Mating End ONLY
Best tin based solution
(>1.3 μm Ni)
Nickel Underplate
SnAgCu &
Nickel Underplate
Sn (matte)
Nickel Underplate
Nickel underplate
required note g
Semi-bright Sn will
not be acceptable
Sn (bright)
Note g
Whisker length Criteria
Min Conductor Spacing
Min Conductor Spacing
Max Whisker Length
Max Whisker Length
(a) Whisker testing includes both mating and PCB mounting end for
(b) Conductor spacing is the minimum tolerance, not nominal value. Supplier
specification must be provided that shows key dimensions including
conductor spacing (nominal +/- tolerance).
(c) Testing will be performed mated to the connector used in application.
Both FPC/FFC and connector (if applicable) will be evaluated for tin whisker.
A matrix shall be provided showing connector / FFC (FPC) combination
(d) Gold / Nickel Underplate is preferred for high reliability applications
(e) Where possible, minimum spacing should be increased to mitigate whisker
(f) High Reliability applications may require testing for spacing above 270um
for any Sn based plating type.
(g) Will be allowed on exception basis only. Exception will be based on
product application and risk. In addition these factors, minimum conductor
spacing must be >270um.
Table 2 – Tin Whisker Test Matrix
Sample Distribution
Full sample size must be provided from each
manufacturing location and solder supplier used. This
includes sub supplier qualification.
Full or partial sample for each bare PCB supplier will be
Agreement regarding sample size and
distribution will be made prior to qualification start.
If different manufacturing lines are used (at time of
evaluation), then sampling must be from each line.
Sampling rate will be determined prior to evaluation.
Distribution of key components from each manufacturer
Key component(s) and build mix will be
determined prior to evaluation.
A control group will be required for comparison purposes.
This control group may consist of the same product
assembled with SnPb solder or previous generation of
SnPb product of same complexity.
2.3 Qualification Requirements – Second level
This level is reserved for products with moderate
perceived risk of failure due to introduction of lead-free
materials and processing. Products determined to be in this
level are more complex and will likely have one or more of
the following surface mounted components: plastic leadless
packages, fine pitch QFPs (≤0.5 mm lead pitch), plastic ball
grid arrays (≤ 27 mm body size) or chip scale packages with
ball pitches ≥1mm (ball pitch of less than 1mm is generally
require solder fatigue evaluation). In addition to the Level 1
requirements of proving process capability and functionality
after assembly, this level of qualification requires testing for
mechanical and thermally induced fatigue failure. This Level
requires that the product also pass qualification Level 1.
2.3.1 Precondition / Assembly
Assembly of product/test boards should be done at
optimum process conditions (including wave or hand solder
when applicable) followed by reworking of predetermined
components on some boards. In some cases exploring
additional assembly conditions may be required. For example,
preconditioning components and boards prior to assembly is
an effective way to prove that worst-case assembly conditions
still produce reliable products (i.e. a sufficiently wide process
window exists). A test plan specific to each product will be
developed and sample sizes for each assembly condition
agreed to prior to testing.
1. Minimum sample sizes for each condition are outlined in
Table 2 for prime and rework. Final sample size is will
depend on testing performed.
2. Assemble components onto boards through the optimum
lead free soldering process.
3. Perform rework of selected components.
4. Prove each component (passive and active) meets
electrical performance specifications either individually
or by functionally testing the entire board.
5. In cases where predetermined IC packages are selected
for preconditioning, follow JEDEC Standard 22-A113D
and expose to level 3 moisture conditions.
Preconditioning boards prior to assembly should take
place per J-STD-003A (8 hr steam age for Sn plated
finish, 35C/85% for 24 hours for OSP finish, and
85°C/85%RH for 12 hours for immersion Ag).
Perform C-SAM and X-ray on key IC package
components after assembly and rework if required.
Minimum sample sizes are shown in Table 2.
7. Visually inspect (with up to 40x magnification) all
components on boards for defects (cracking,
delamination, etc.) and record all observations. Provide
component inspection standards (i.e. pass/fail criteria)
used for this inspection.
8. Visually inspect (with up to 40x magnification) solder
joints for defects. Inspection standard IPC-A-610D.
9. To establish a baseline prior to reliability testing, major
components on at least PCBA should be cross sectioned
after assembly while those on another PCBA should be
subjected to Die & Pry. Inner-metallic layer thickness
should be in the range of 1-2um.
10. Criteria: Component delamination from C-SAM must
meet criteria according to J-STD-020C. Zero electrical
failures are allowed. No critical soldering defects
(voiding should be less than 25% of joint area as revealed
in X-ray inspection).
11. Use these assembled boards for reliability tests according
to test plan.
12. Test and failure analysis results will be provided
2.3.2 Vibration and Shock
Concurrent testing for both vibration and shock shall be
performed when determined to be necessary. Testing details
will be prescribed according to the product type and expected
use environment. Typical tests may include non-operational
vibration followed by shipping shock (pack drop). In some
instances mechanical shock and vibration testing may be
preceded by thermal shock. Operational testing in a system
level may also be performed. Sample sizes and pass/fail
criteria will be determined during creation of the detailed test
plan (sample size will typically be 5 or greater for each test
2.3.3 Thermal Cycling
This testing is required primarily for level 2 components.
Follow procedures described in JESD22-A104-B, condition J.
The specific requirements described below fit many product
types, however, alternative thermal cycling test protocols and
evaluation plans are potentially acceptable.
1. Sample size ≥ 20. A separate group of an additional 10
reworked components will also undergo thermal cycle (if
2. The complete functional PCBA must be thermal cycle
3. Cycle 1000 times from 0 to 100°C with a ramp rate of 1020°C/min and a 10 min dwell time (measure temperature
on the largest thermal mass component on the PCB).
4. Visually inspect joints and confirm functionality of
complete PCBAs after 500 and 1000 cycles.
5. In cases where proving electrical functionality is not
feasible, solder joints on BGA components can be
evaluated after 1000 cycles using dye and pry.
6. Criteria: Zero solder joint failures accepted unless product
life requirements allow for a failure.
a. A failure is defined by a functional test error or a
joint that is cracked 50% through (as revealed by dye
and pry).
b. Visual inspection and functional test specifics to be
agreed upon prior to commencement of test.
Additional evaluation may include cross sectioning,
lead pull, and component shear. Issues found during
additional evaluation, including visual inspection,
will be reviewed prior to determination of product
Test and failure analysis results will be provided. Solder
joint failures will be assessed and corrective actions
2.3.4 Highly Accelerated Life Testing (HALT)
Listed below are minimum acceptable test conditions
according to current practice.
1. HALT is primarily a board level test that must be
performed within a multi-stress (temperature and
vibration) chamber.
2. During the HALT process, thermal cycling and vibration
are to be simultaneously applied.
3. The temperature responses on critical components must
be monitored with thermocouples to insure adequacy of
the dwell periods selected.
4. The temperature range (between highest and lowest dwell
temperatures) is to be a minimum of 80-degrees C unless
otherwise technology limited.
5. The product is to be functionally operational and
monitored during “HALT” stressing.
6. Sample size preferred is 2 units.
7. Where a previously established baseline is available, the
product must meet or exceed prior limits. Where no prior
baseline is established, comparative results to leaded
control sample must be met.
8. Supplier conducted HALT must include reporting test
results according to agreed upon format, including full
failure analysis and corrective action on anomalies
9. Criteria: Component delamination must meet criteria
according to J-STD-020C. Zero functional failures, or
fully cracked solder joints.
Converting to lead-free products and processes introduces
many risks some of which are better understood than others.
This paper has explored the main risks involved and showed
how to evaluate the risks and set up qualification programs to
mitigate these risks. If these steps are taken, the reliability of
lead-free products and processes can yield products just as
reliable as their leaded counterparts.
Statuatory Instrument 2006 No. 1463, Environmental
Protection, The Restriction of the Use of Certain
Hazardous Substances in Electrical and Electronic
Equipment Regulations, 2006.
Mike Silverman, CRE
Ops A La Carte, LLC
20151 Guava Court
Saratoga, CA 95070 USA
e-mail: [email protected]
Mike is founder and managing partner at Ops A La Carte, a
Professional Business Operations Company that offers a broad
array of expert services in support of new product
development and production initiatives. The primary set of
services currently being offered are in the area of reliability.
Through Ops A La Carte, Mike has had extensive experience
as a consultant to high-tech companies, and has consulted for
over 200 companies including Cisco, Ciena, Apple, Siemens,
Intuitive Surgical, Abbott Labs, and Applied Materials. He
has consulted in a variety of different industries including
telecommunications, networking, medical, semiconductor,
semiconductor equipment, consumer electronics, and defense
electronics. Mike has 25 years of reliability, quality, and
compliance experience, the majority in start-up companies.
He is also an expert in accelerated reliability techniques,
including HALT and HASS. He set up and ran an accelerated
reliability test lab for 5 years, testing over 300 products for
100 companies in 40 different industries. Mike has authored
and published 8 papers on reliability techniques and has
presented these around the world including China, Germany,
and Canada. He has also developed and currently teaches 8
courses on reliability techniques. Mike has a BS degree in
Electrical and Computer Engineering from the University of
Colorado at Boulder, and is both a Certified Reliability
Engineer and a course instructor through the American
Society for Quality (ASQ), IEEE, and Effective Training
Associates. Mike is a member of ASQ, IEEE, SME, ASME,
PATCA, and IEEE Consulting Society. Currently he is the
IEEE Reliability Society Santa Clara Valley Chapter Chair
and the IEEE Consultants’ Society Santa Clara Valley Chapter
Vice Chair.
Fred Schenkelberg, CRE, CQE
Ops A La Carte, LLC
20151 Guava Court
Saratoga, CA 95070 USA
e-mail: [email protected]
Fred Schenkelberg is a Senior Reliability Engineering
Consultant at Ops A La Carte. He is currently working with
clients using reliability assessments as a starting point to
develop and execute detailed reliability plans and programs.
Also, he exercises his reliability engineering and statistical
knowledge to design and conduct accelerated life tests. Fred
has conducted over 75 assessments in 20 different industries
around the world. Fred has an excellent knowledge in
reliability techniques across the entire product life cycle and
has specific expertise in Accelerated Life Testing (ALT),
Restriction of Hazardous Substances (RoHS/WEEE/Lead-Free
Compliance), and Warranty Analysis/Improvement. Fred has
developed and performed Accelerated Life Tests for
Mechanical, Electrical, Chemical, and a combination of each
of these types of products for over 50 different companies in
20 different industries. Fred sat on several national workshops
for 2 years and has developed a methodology for creating
RoHS-specific tailored Reliability Test Plans. Fred copresented with Eric Arnum, editor of “Warranty Week
Magazine” and has chaired sessions at the Warranty Chain
Management Symposium for the past 2 years. Fred is also an
accomplished trainer, educator, facilitator, mentor, and coach.
He has developed training courses in over a dozen different
disciplines within reliability and has trained thousands of
engineers and managers in a variety of reliability topics in
various industries. Fred joined HP in February 1996 in
Vancouver, WA. He joined HP’s ESTC Group in Palo Alto,
CA., in January 1998 and co-founded the HP Product
Reliability Team. He was responsible for the community
building, consulting and training aspects of the Product
Reliability Program. He was also responsible for research and
development on selected product reliability management
topics. Prior to joining HP ESTC, he worked as a design for
manufacturing engineer on DeskJet printers. Before HP he
worked with Raychem Corporation in various positions,
including research and development of accelerated life testing
of polymer based heating cables. He has a Bachelors of
Science in Physics from the United States Military Academy
and a Masters of Science in Statistics from Stanford
University. Fred has been an active member of the RAMS
Mgmt. Committee for 4 years, on the ASQ National
Committee for 2 years, and an officer with IEEE Reliability
Society Santa Clara Chapter for 5 years.
Craig Hillman, PhD
DfR Solutions
5110 Roanoke Pl. Ste. 101
College Park, MD 20740 USA
e-mail: [email protected]
Dr. Hillman‘s specialties include best practices in Design for
Reliability (DfR), strategies for transitioning to Pb-free,
supplier qualification (commodity and engineered products),
passive component technology (capacitors, resistors, etc.), and
printed board failure mechanisms. Dr. Hillman has over 40
publications and has presented on a wide variety of reliability
issues to over 200 companies and organizations. Dr. Hillman
received his Post-doctoral fellowship from Cambridge
University, his PhD in Materials from University of California
Santa Barbara, and his B.S. in Metallurgical Engineering and
Material Science from Carnegie Mellon.