This tutorial explains how to simulate a behavioral code using NCLaunch. In order to do so,
let’s consider the verilog codes below.
CNT_16 Module:
16 bit up counter with asynchronous active-low reset
`timescale 1ns/1ps
module CNT_16(CLK, RSTB, OUT);
input CLK, RSTB;
output [15:0] OUT;
reg [15:0] OUT;
[email protected](posedge CLK or negedge RSTB) begin
if(!RSTB) begin
OUT <= 0;
else begin
OUT <= OUT + 1;
CMP_16 Module:
Comparator which compares the 16 bit input with 50.
`timescale 1ns/1ps
module CMP_16(IN, OUT);
input [15:0] IN;
output OUT;
reg OUT;
[email protected](IN) begin
if(IN <= 50) begin
OUT = 0;
else begin
OUT = 1;
TOP Module:
The top module which connects both. The resulting design makes OUT=1 after 50 clock
`timescale 1ns/1ps
module TOP(CLK, RSTB, OUT);
input CLK, RSTB;
output OUT;
wire [15:0] OUT_16;
CMP_16 U1(OUT_16, OUT);
CNT_16 U2(CLK, RSTB, OUT_16);
TEST_TOP Module:
Testbench module to test the top module.
`timescale 1ns/1ps
module TEST_TOP;
reg CLK, RSTB;
wire OUT;
initial begin
RSTB = 0;
CLK = 0;
#3 RSTB = 1;
#10000 $finish;
always #5 CLK = ~CLK;
To start behavioral simulation, let’s make a new folder.
Then let’s copy all Verilog files to newly created folder.
Launch NCLaunch program with nclaunch –new command. If we had run a simulation in the
folder before that we want to go back to, we should simply use nclaunch command.
Let’s choose Multiple Step for step by step compilation, elaboration and simulation. Single
Step makes all these three in one step.
In order to initialize NCLaunch, we need a cds.lib file. Let’s click on Create cds.lib File
And save newly created cds.lib file into our simulation folder.
When asked for which libraries to include, select Don’t include any libraries for verilog
Now our cds.lib is created. Let’s click OK
The NCLaunch window looks like this. Left panel is the directory which includes the verilog
files. Right side is the design hierarchy. worklib is the library which includes our compiled
designs and Snapshots is the folder which includes our elaborated testbenches.
Let’s select the verilog files from the left panel and click Launch Verilog Compiler icon.
Alternatively we can double click on each file to compile.
If there are no errors, the compiled designs are shown under the worklib.
Let’s click on testbench module TEST_TOP and click Launch Elaborator icon to elaborate
the testbench.
Elaborated testbench module is shown under Snapshots. Let’s select that module and click
Launch Simulator icon.
The simulator program SimVision opens. From the Design Browser window, let’s select the
design to see the waveform names.
Let’s select waveforms then click Send to Waveform window icon.
Now we can see the waveform names in the left pane. Let’s click Run the simulation icon.
Let’s click Zoom Out icon to see more of our waveforms.
Let’s check whether the value of the counter is 50 when OUT goes high. In order to add the
output of the counter to the waveform window, let’s click on Browse the design hierarchy
The OUT_16 wire of TOP module would to the trick, so let’s find and select the new
waveform to be added. Just clicking on the wire name will add it to the waveform window.
Next, let’s click on Collapse the Design Browser to get rid of Design Browser.
As we can see, the newly added waveform is empty. In order to see the waveform, we should
run the simulation again. In order to do so, let’s click on Reset the simulation icon
Now let’s click on the Run the simulation icon once again.
Then zoom out once again to see more.
Since we humans can understand decimal digits easier, let’s right click on the cursor column
and select Decimal in Radix/Mnemonic tab.
As we can see, the OUT goes high when the counter hits 50, so the design works as expected.
Now let’s change the design a little bit. Let’s return to NCLaunch window and right click on
CMP_16 submodule, then select Edit.
Let’s change the compared value from 50 to 40.
After we save the file and exit from the editor, we can see that icons of some designs in the
right panel have a little clock, which means that they are outdated. In order to update them,
let’s right click on the elaborated testbench and select Update.
Then click OK
All design files are now updated. As we can see, updating elaborated testbench is enough to
update all submodules.
To simulate our new design, we can close the SimVision and launch it again from NCLaunch.
But if we do that, out waveform selections and waveform configurations such as selecting
decimal radix of OUT_16 will be lost. So, in order to make things faster, let’s click on
Reinvoke Simulator from the Simulation menu of SimVision.
Let’s click Yes to reinvoke simulator
Let’s start the simulation again by clicking on Run the simulation icon.
As we can see, the new design works as expected. The OUT goes high when the counter hits