“How To” create the PLLJ_PLLSPE_INFO.txt report when your

“How To” create the PLLJ_PLLSPE_INFO.txt report when your
project uses the Classic Timing Analyzer
The TimeQuest Timing Analyzer can create a report file which includes the static phase minimum
and maximum offset value as well as the deterministic jitter for each PLL in a Quartus® II
software project targeting FPGA families beginning with Stratix® II, Cyclone® III and Arria® GX
device families. This document shows the steps required to generate this report with minimal
TimeQuest interaction for projects that use the Classic Timing Analyzer flow.
1) Compile your project in Quartus II software.
2) Open the TimeQuest Timing Analyzer. This can be done by using the TimeQuest Timing
Analyzer icon in the Quartus II GUI, or selecting TimeQuest Timing Analyzer in the Tools menu.
3) When TimeQuest opens, you will see a message saying “No SDC files were found in the
Quartus Settings File and <project_name>.sdc doesn’t exist. Would you like to generate an SDC
file from the Quartus Settings File?”
Select “Yes”.
4) If you do not get the message box in step (3), you can quickly generate an SDC file by
selecting “Generate SDC file from QSF” from the Constraints menu.
5) Select File – Open SDC File. You should see a file <project_name>.sdc. Select that file. This
is a skeleton SDC constraint file created based on the current settings from your Quartus II
6) Insert the following SDC command in the file – “derive_clock_uncertainty”. It is best to insert
this text after the create_clock and derive_PLL_clocks command to follow a logical flow in the
SDC file, but the location of this command does not matter from a technical standpoint.
7) Select File – Save and then close the SDC file.
8) Close the TimeQuest Timing Analyzer.
9) In Quartus II, go to the Assignments – Settings menu and select Timing Analysis Settings from
the Category list. Select “Use TimeQuest Timing Analyzer during compilation”.
10) In the Category list, select TimeQuest Timing Analyzer. This opens the TimeQuest Timing
Analyzer options.
11) Click the button next to “SDC filename:” in the in the “SDC files to include in the project”.
Select your <project_name>.sdc file and add it here.
The <project_name>.sdc should now appear in the “file name” box. Select “ok” to close this
options box.
12) In Quartus II, select “Start TimeQuest Timing Analyzer” either by selecting the icon in the
GUI, or in the Processing - Start menu.
13) In Quartus II, select the File menu and type *.txt in the File Name box. You will see
“PLLJ_PLLSPE_INFO.txt” appear. Open this file, either in Quartus II or in a text editor to view the
deterministic jitter, static phase error max value, and the static phase error min value for each
PLL in your design. Note, the deterministic jitter is just the intrinsic jitter of the PLL, it does not
consider jitter transfer from the clock source.
14) Repeat step 9, but select “Use Classic Timing Analyzer during compilation” to restore your
project back to using the Classic Timing Analyzer.